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	XC9572-15PC84I
	Xilinx,
	XC9572 In-System Programmable CPLD
	60.309 千字节
	8 页
	Maker Site: http://www.xilinx.com
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XC9572-15PC84I DataSheet Xilinx, Inc XC9572 In-System Programmable CPLD

---Full Text Search Engine--- XC9572-15PC84I Xilinx, ---Full Text Search Engine--- XC9572 In-System Programmable CPLD

	XC9572-10TQ100I XC9572-15TQ100I XC9572-15TQ100I XC9572-15TQ100C XC9572-10BPQ100I XC9572-15BPQ100I XC9572-7BPQ100C XC9572-7BPQ100I XC9572 XC9572-15PQ100C XC9572-15PQ100I XC9572-10PC44I XC9572-10PC84C XC9572-10PC44 XC9572-10PC44C XC9572-10PC84I XC9572-15PC44I XC9572-15PC84I XC9572-15PC84C XC9572-10TQ100C XC9572-10TQ100I
	1 (R) XC9572 In-System Programmable CPLD 1 1* December 4, 1998 (Version 3.0) Product Specification Features * * * * * 7.5 ns pin-to-pin logic delays on all pins fCNT to 125 MHz 72 macrocells with 1,600 usable gates Up to 72 user I/O pins 5 V in-system programmable (ISP) - Endurance of 10,000 program/erase cycles - Program/erase over full commercial voltage and temperature range Enhanced pin-locking architecture Flexible 36V18 Function Block - 90 product terms drive any or all of 18 macrocells within Function Block - Global and product term clocks, output enables, set and reset signals Extensive IEEE Std 1149.1 boundary-scan (JTAG) support Programmable power reduction mode in each macrocell Slew rate control on individual outputs User programmable ground pin capability Extended pattern security features for design protection High-drive 24 mA outputs 3.3 V or 5 V I/O capability Advanced CMOS 5V FastFLASH technology Supports parallel programming of more than one XC9500 concurrently Available in 44-pin PLCC, 84-pin PLCC, 100-pin PQFP and 100-pin TQFP packages Power Management Power dissipation can be reduced in the XC9572 by configuring macrocells to standard or low-power modes of operation. Unused macrocells are turned off to minimize power dissipation. Operating current for each design can be approximated for specific operating conditions using the following equation: ICC (mA) = MCHP (1.7) + MCLP (0.9) + MC (0.006 mA/MHz) f Where: MCHP = Macrocells in high-performance mode MCLP = Macrocells in low-power mode MC = Total number of macrocells used f = Clock frequency (MHz) Figure 1 shows a typical calculation for the XC9572 device. * * * * * * * * * * * * 200 erform High P Typical Icc (ma) a n ce (160) (125) 100 o we r Low P (100) Description The XC9572 is a high-performance CPLD providing advanced in-system programming and test capabilities for general purpose logic integration. It is comprised of four 36V18 Function Blocks, providing 1,600 usable gates with propagation delays of 7.5 ns. See Figure 2 for the architecture overview. (65) 0 50 Clock Frequency (MHz) 100 Figure 1: Typical ICC vs. Frequency for XC9572 December 4, 1998 (Version 3.0) 1 XC9572 In-System Programmable CPLD 3 JTAG Port 1 JTAG Controller In-System Programming Controller 36 I/O I/O I/O I/O FastCONNECT Switch Matrix 36 18 18 Function Block 1 Macrocells 1 to 18 Function Block 2 Macrocells 1 to 18 I/O Blocks I/O I/O I/O I/O 3 I/O/GCK 1 I/O/GSR I/O/GTS 2 36 18 Function Block 3 Macrocells 1 to 18 36 18 Function Block 4 Macrocells 1 to 18 X5921 Figure 2: XC9572 Architecture Note: Function Block outputs (indicated by the bold line) drive the I/O Blocks directly 2 December 4, 1998 (Version 3.0) XC9572 In-System Programmable CPLD Absolute Maximum Ratings Symbol VCC VIN VTS TSTG TSOL Parameter Supply voltage relative to GND DC input voltage relative to GND Voltage applied to 3-state output with respect to GND Storage temperature Max soldering temperature (10 s @ 1/16 in = 1.5 mm) Value -0.5 to 7.0 -0.5 to VCC + 0.5 -0.5 to VCC + 0.5 -65 to +150 +260 Units V V V C C Warning: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions is not implied. Exposure to Absolute Maximum Rating conditions for extended periods of time may affect device reliability. Recommended Operation Conditions Symbol VCCINT VCCIO VIL VIH VO Parameter 1 Min 4.75 (4.5) 4.75 (4.5) 3.0 0 2.0 0 Max 5.25 (5.5) 5.25 (5.5) 3.6 0.80 VCCINT +0.5 VCCIO Units V V V V V V Supply voltage for internal logic and input buffer Supply voltage for output drivers for 5 V operation Supply voltage for output drivers for 3.3 V operation Low-level input voltage High-level input voltage Output voltage Note: 1. Numbers in parenthesis are for industrial temperature range versions. Endurance Characteristics Symbol tDR NPE Data Retention Program/Erase Cycles Parameter Min 20 10,000 Max Units Years Cycles December 4, 1998 (Version 3.0) 3 XC9572 In-System Programmable CPLD DC Characteristics Over Recommended Operating Conditions Symbol VOH Parameter Output high voltage for 5 V operation Output high voltage for 3.3 V operation VOL Output low voltage for 5 V operation Output low voltage for 3.3 V operation IIL IIH CIN ICC Input leakage current I/O high-Z leakage current I/O capacitance Operating Supply Current (low power mode, active) Test Conditions IOH = -4.0 mA VCC = Min IOH = -3.2 mA VCC = Min IOL = 24 mA VCC = Min IOL = 10 mA VCC = Min VCC = Max VIN = GND or VCC VCC = Max VIN = GND or VCC VIN = GND f = 1.0 MHz VI = GND, No load f = 1.0 MHz Min 2.4 2.4 0.5 0.4 10.0 10.0 10.0 65 (Typ) Max Units V V V V A A pF ma AC Characteristics Symbol tPD tSU tH tCO fCNT1 fSYSTEM 2 tPSU tPH tPCO tOE tOD tPOE tPOD tWLH Parameter I/O to output valid I/O setup time before GCK I/O hold time after GCK GCK to output valid 16-bit counter frequency Multiple FB internal operating frequency I/O setup time before p-term clock input I/O hold time after p-term clock input P-term clock to output valid GTS to output valid GTS to output disable Product term OE to output enabled Product term OE to output disabled GCK pulse width (High or Low) XC9572-7 Min 4.5 0.0 4.5 125.0 83.3 0.5 4.0 8.5 5.5 5.5 9.5 9.5 4.0 4.5 111.1 66.7 2.0 4.0 10.0 6.0 6.0 10.0 10.0 5.5 Max 7.5 6.0 0.0 6.0 95.2 55.6 4.0 4.0 12.0 11.0 11.0 14.0 14.0 XC9572-10 Min Max 10.0 8.0 0.0 8.0 XC9572-15 Min Max 15.0 Units ns ns ns ns MHz MHz ns ns ns ns ns ns ns ns Note: 1. fCNT is the fastest 16-bit counter frequency available, using the local feedback when applicable. fCNT is also the Export Control Maximum flip-flop toggle rate, fTOG. 2. fSYSTEM is the internal operating frequency for general purpose system designs spanning multiple FBs. VTEST R1 Device Output R2 CL Output Type VCCIO 5.0 V 3.3 V VTEST 5.0 V 3.3 V R1 160 260 R2 120 360 CL 35 pF 35 pF X5906 Figure 3: AC Load Circuit 4 December 4, 1998 (Version 3.0) XC9572 In-System Programmable CPLD Internal Timing Parameters Symbol Parameter XC9572-7 Min Max 2.5 1.5 4.5 5.5 2.5 0.0 3.0 2.0 4.5 0.5 1.5 3.0 0.5 6.5 7.5 2.0 10.0 8.0 4.0 1.0 4.0 10.0 2.5 11.0 9.5 3.5 1.0 4.5 2.5 3.5 0.5 7.0 10.0 3.0 11.5 11.0 3.5 1.0 5.0 XC9572-10 Min Max 3.5 2.5 6.0 6.0 3.0 0.0 3.0 2.5 3.5 1.0 3.5 4.5 0.5 8.0 XC9572-15 Min Max 4.5 3.0 7.5 11.0 4.5 0.0 2.5 3.0 5.0 3.0 Units Buffer Delays tIN Input buffer delay tGCK GCK buffer delay tGSR GSR buffer delay tGTS GTS buffer delay tOUT Output buffer delay tEN Output buffer enable/disable delay Product Term Control Delays tPTCK Product term clock delay tPTSR Product term set/reset delay tPTTS Product term 3-state delay Internal Register and Combinatorial delays tPDI Combinatorial logic propagation delay tSUI Register setup time tHI Register hold time tCOI Register clock to output valid time tAOI Register async. S/R to output delay tRAI Register async. S/R recovery before clock tLOGI Internal logic delay tLOGILP Internal low power logic delay Feedback Delays tF FastCONNECT matrix feedback delay tLF Function Block local feeback delay Time Adders tPTA3 Incremental Product Term Allocator delay tSLEW Slew-rate limited delay ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Note: 3. tPTA is multiplied by the span of the function as defined in the family data sheet. December 4, 1998 (Version 3.0) 5 XC9572 In-System Programmable CPLD XC9572 I/O Pins Function Macrocell Block PC 44 PC 84 PQ 100 TQ 100 BScan Notes Order Function Macrocell Block PC 44 PC 84 PQ 100 TQ 100 BScan Notes Order 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 - 1 - - 2 3 - 4 5 - 6 - - 7 8 - 9 - - 35 - - 36 37 - 38 39 - 40 - - 42 43 - 44 - 4 1 6 7 2 3 11 5 9 13 10 18 20 12 14 23 15 24 63 69 67 68 70 71 76 72 74 75 77 79 80 81 83 82 84 - 18 15 20 22 16 17 27 19 24 30 25 35 38 29 31 41 32 42 89 96 93 95 97 98 5 99 1 3 6 8 10 11 13 12 14 94 16 13 18 20 14 15 25 17 22 28 23 33 36 27 29 39 30 40 87 94 91 93 95 96 3 97 99 1 4 6 8 9 11 10 12 92 213 210 207 204 201 198 195 192 189 186 183 180 177 174 171 168 165 162 159 156 153 150 147 144 141 138 135 132 129 126 123 120 117 114 111 108 [1] [1] [1] [2] [1] [1] [3] 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 - 11 - - 12 - - 13 14 - 18 - - 19 20 - 22 - - 24 - - 25 - - 26 27 - 28 - - 29 33 - 34 - 25 17 31 32 19 34 35 21 26 40 33 41 43 36 37 45 39 - 46 44 51 52 47 54 55 48 50 57 53 58 61 56 65 62 66 - 43 34 51 52 37 55 56 39 44 62 54 63 65 57 58 67 60 61 68 66 73 74 69 78 79 70 72 83 76 84 87 80 91 88 92 81 41 32 49 50 35 53 54 37 42 60 52 61 63 55 56 65 58 59 66 64 71 72 67 76 77 68 70 81 74 82 85 78 89 86 90 79 105 102 99 96 93 90 87 84 81 78 75 72 69 66 63 60 57 54 51 48 45 42 39 36 33 30 27 24 21 18 15 12 9 6 3 0 Notes: [1] Global control pin [2] Global control pin GTS1 for PC84, PQ100, and TQ100 [3] Global control pin GTS1 for PC44 6 December 4, 1998 (Version 3.0) XC9572 In-System Programmable CPLD XC9572 Global, JTAG and Power Pins Pin Type I/O/GCK1 I/O/GCK2 I/O/GCK3 I/O/GTS1 I/O/GTS2 I/O/GSR TCK TDI TDO TMS VCCINT 5 V VCCIO 3.3 V/5 V GND No Connects PC44 5 6 7 42 40 39 17 15 30 16 21,41 32 10,23,31 - PC84 9 10 12 76 77 74 30 28 59 29 38,73,78 22,64 8,16,27,42, 49,60 -- PQ100 24 25 29 5 6 1 50 47 85 49 7,59,100 28,40,53,90 2,23,33,46,64,71, 77,86 4,9,21,26,36,45,48, 75, 82 TQ100 22 23 27 3 4 99 48 45 83 47 5,57,98 26,38,51,88 100,21,31,44,62,69, 75, 84 2,7,19,24,34,43,46, 73, 80 December 4, 1998 (Version 3.0) 7 XC9572 In-System Programmable CPLD Ordering Information XC9572 -7 PQ 100 C Device Type Speed Temperature Range Number of Pins Package Type Speed Options -15 15 ns pin-to-pin delay -10 10 ns pin-to-pin delay -7 7.5 ns pin-to-pin delay Packaging Options PC44 PC84 PQ100 TQ100 44-Pin Plastic Leaded Chip Carrier (PLCC) 84-Pin Plastic Leaded Chip Carrier (PLCC) 100-Pin Plastic Quad Flat Pack (PQFP) 100-Pin Very Thin Quad Flat Pack (TQFP) Temperature Options C I Commercial0C to +70C Industrial-40C to +85C Component Availability Pins Type Code XC9572 -15 -10 -7 44 Plastic PLCC PC44 C(I) C(I) C 84 Plastic PLCC PC84 C(I) C(I) C 100 Plastic PQFP PQ100 C(I) C(I) C Plastic TQFP TQ100 C(I) C(I) C C = Commercial = 0 to +70C I = Industrial = -40 to +85C Revision Control Date 12/04/98 Revision Update AC Characteristics and Internal Parameters 8 December 4, 1998 (Version 3.0)

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