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	SN74LVC2T45YZPR

	DUAL-BIT DUAL-SUPPLY TRANSCEIVER WITH CONFIGURABLE VOLTAGE TRANSLATION 3-STATE OUTPUTS
	494.319 千字节
	23 页

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SN74LVC2T45YZPR DataSheet TI DUAL-BIT DUAL-SUPPLY BUS TRANSCEIVER WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS

---Full Text Search Engine--- SN74LVC2T45YZPR ---Full Text Search Engine--- DUAL-BIT DUAL-SUPPLY TRANSCEIVER WITH CONFIGURABLE VOLTAGE TRANSLATION 3-STATE OUTPUTS

	SN74LVC2T45YZPR SN74LVC2T45_07 SN74LVC2T45 SN74LVC2T45DCTR SN74LVC2T45DCTRE4 SN74LVC2T45DCTT SN74LVC2T45DCTTE4 SN74LVC2T45DCUR SN74LVC2T45DCURE4 SN74LVC2T45DCURG4 SN74LVC2T45DCUT SN74LVC2T45DCUTE4 SN74LVC2T45YZPR
	SN74LVC2T45 DUAL-BIT DUAL-SUPPLY BUS TRANSCEIVER WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS www.ti.com SCES516I - DECEMBER 2003 - REVISED MARCH 2007 FEATURES * * Available in the Texas Instruments NanoFreeTM Package Fully Configurable Dual-Rail Design Allows Each Port to Operate Over the Full 1.65-V to 5.5-V Power-Supply Range VCC Isolation Feature - If Either VCC Input Is at GND, Both Ports Are in the High-Impedance State DIR Input Circuit Referenced to VCCA Low Power Consumption, 10-A Max ICC 24-mA Output Drive at 3.3 V Ioff Supports Partial-Power-Down Mode Operation Max Data Rates - 420 Mbps (3.3-V to 5-V Translation) - 210 Mbps (Translate to 3.3 V) - 140 Mbps (Translate to 2.5 V) - 75 Mbps (Translate to 1.8 V) Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Protection Exceeds JESD 22 - 4000-V Human-Body Model (A114-A) - 200-V Machine Model (A115-A) - 1000-V Charged-Device Model (C101) DCT OR DCU PACKAGE (TOP VIEW) * VCCA A1 A2 GND 1 2 3 4 8 7 6 5 VCCB B1 B2 DIR * * * * * YZP PACKAGE (BOTTOM VIEW) GND A2 A1 VCCA D1 C1 B1 A1 45 3 6 D2 C2 B2 A2 DIR B2 B1 VCCB 27 18 * * DESCRIPTION/ORDERING INFORMATION This dual-bit noninverting bus transceiver uses two separate configurable power-supply rails. The A port is designed to track VCCA. VCCA accepts any supply voltage from 1.65 V to 5.5 V. The B port is designed to track VCCB. VCCB accepts any supply voltage from 1.65 V to 5.5 V. This allows for universal low-voltage bidirectional translation between any of the 1.8-V, 2.5-V, 3.3-V, and 5-V voltage nodes. ORDERING INFORMATION TA PACKAGE (1) NanoFree - WCSP (DSBGA) 0.23-mm Large Bump - YZP (Pb-free) -40C to 85C SSOP - DCT VSSOP - DCU (1) (2) Reel of 3000 Reel of 3000 Reel of 250 Reel of 3000 Reel of 250 ORDERABLE PART NUMBER SN74LVC2T45YZPR SN74LVC2T45DCTR SN74LVC2T45DCTT SN74LVC2T45DCUR SN74LVC2T45DCUT TOP-SIDE MARKING (2) _ _ _TB_ CT2_ _ _ CT2_ For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. DCT: The actual top-side marking has three additional characters that designate the year, month, and assembly/test site. DCU: The actual top-side marking has one additional character that designates the assembly/test site. YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, * = Pb-free). Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. NanoFree is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 2003-2007, Texas Instruments Incorporated SN74LVC2T45 DUAL-BIT DUAL-SUPPLY BUS TRANSCEIVER WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS SCES516I - DECEMBER 2003 - REVISED MARCH 2007 www.ti.com DESCRIPTION/ORDERING INFORMATION (CONTINUED) The SN74LVC2T45 is designed for asynchronous communication between two data buses. The logic levels of the direction-control (DIR) input activate either the B-port outputs or the A-port outputs. The device transmits data from the A bus to the B bus when the B-port outputs are activated, and from the B bus to the A bus when the A-port outputs are activated. The input circuitry on both A and B ports always is active and must have a logic HIGH or LOW level applied to prevent excess ICC and ICCZ. The SN74LVC2T45 is designed so that the DIR input circuit is supplied by VCCA. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The VCC isolation feature ensures that if either VCC input is at GND, both ports are in the high-impedance state. NanoFreeTM package technology is a major breakthrough in IC packaging concepts, using the die as the package. FUNCTION TABLE (1) (EACH TRANSCEIVER) INPUT DIR L H (1) OPERATION B data to A bus A data to B bus Input circuits of the data I/Os always are active. LOGIC DIAGRAM (POSITIVE LOGIC) DIR 5 A1 2 7 B1 A2 3 6 B2 VCCA VCCB 2 Submit Documentation Feedback www.ti.com SN74LVC2T45 DUAL-BIT DUAL-SUPPLY BUS TRANSCEIVER WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS SCES516I - DECEMBER 2003 - REVISED MARCH 2007 (1) Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) MIN VCCA VCCB VI VO VO IIK IOK IO Supply voltage range Input voltage range (2) Voltage range applied to any output in the high-impedance or power-off state (2) Voltage range applied to any output in the high or low state (2) (3) Input clamp current Output clamp current Continuous output current Continuous current through VCC or GND DCT package JA Tstg (1) (2) (3) (4) Package thermal impedance (4) Storage temperature range DCU package YZP package -65 A port B port VI < 0 VO < 0 -0.5 -0.5 -0.5 -0.5 -0.5 MAX 6.5 6.5 6.5 VCCA + 0.5 VCCB + 0.5 -50 -50 50 100 220 227 102 150 C C/W UNIT V V V V mA mA mA mA Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. The value of VCC is provided in the recommended operating conditions table. The package thermal impedance is calculated in accordance with JESD 51-7. Submit Documentation Feedback 3 SN74LVC2T45 DUAL-BIT DUAL-SUPPLY BUS TRANSCEIVER WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS SCES516I - DECEMBER 2003 - REVISED MARCH 2007 www.ti.com Recommended Operating Conditions (1) (2) (3) VCCI VCCA VCCB Supply voltage 1.65 V to 1.95 V VIH High-level input voltage Data inputs (4) 2.3 V to 2.7 V 3 V to 3.6 V 4.5 V to 5.5 V 1.65 V to 1.95 V VIL Low-level input voltage Data inputs (4) 2.3 V to 2.7 V 3 V to 3.6 V 4.5 V to 5.5 V 1.65 V to 1.95 V VIH High-level input voltage DIR (referenced to VCCA) (5) 2.3 V to 2.7 V 3 V to 3.6 V 4.5 V to 5.5 V 1.65 V to 1.95 V VIL Low-level input voltage DIR (referenced to VCCA) (5) 2.3 V to 2.7 V 3 V to 3.6 V 4.5 V to 5.5 V VI VO Input voltage Output voltage 1.65 V to 1.95 V IOH High-level output current 2.3 V to 2.7 V 3 V to 3.6 V 4.5 V to 5.5 V 1.65 V to 1.95 V IOL Low-level output current 2.3 V to 2.7 V 3 V to 3.6 V 4.5 V to 5.5 V 1.65 V to 1.95 V t/v Input transition rise or fall rate Data inputs 2.3 V to 2.7 V 3 V to 3.6 V 4.5 V to 5.5 V Control input TA (1) (2) (3) (4) (5) Operating free-air temperature 1.65 V to 5.5 V -40 0 0 VCCA x 0.65 1.7 2 VCCA x 0.7 VCCA x 0.35 0.7 0.8 VCCA x 0.3 5.5 VCCO -4 -8 -24 -32 4 8 24 32 20 20 10 5 5 85 C ns/V mA mA V V V V VCCO MIN 1.65 1.65 VCCI x 0.65 1.7 2 VCCI x 0.7 VCCI x 0.35 0.7 0.8 VCCI x 0.3 V V MAX 5.5 5.5 UNIT V VCCI is the VCC associated with the input port. VCCO is the VCC associated with the output port. All unused data inputs of the device must be held at VCCI or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. For VCCI values not specified in the data sheet, VIH min = VCCI x 0.7 V, VIL max = VCCI x 0.3 V. For VCCI values not specified in the data sheet, VIH min = VCCA x 0.7 V, VIL max = VCCA x 0.3 V. 4 Submit Documentation Feedback www.ti.com SN74LVC2T45 DUAL-BIT DUAL-SUPPLY BUS TRANSCEIVER WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS SCES516I - DECEMBER 2003 - REVISED MARCH 2007 (1) (2) Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS IOH = -100 A IOH = -4 mA VOH IOH = -8 mA IOH = -24 mA IOH = -32 mA IOL = 100 A IOL = 4 mA VOL IOL = 8 mA IOL = 24 mA IOL = 32 mA II Ioff IOZ DIR A port B port A or B port VI = VCCA or GND VI or VO = 0 to 5.5 V VO = VCCO or GND VI = VIL VI = VIH VCCA 1.65 V to 4.5 V 1.65 V 2.3 V 3V 4.5 V 1.65 V to 4.5 V 1.65 V 2.3 V 3V 4.5 V 1.65 V to 5.5 V 0V 0 to 5.5 V 1.65 V to 5.5 V 1.65 V to 5.5 V ICCA VI = VCCI or GND, IO = 0 5V 0V 1.65 V to 5.5 V ICCB ICCA + ICCB (see Table 1) A port ICCA DIR ICCB CI Cio (1) (2) B port DIR A or B port VI = VCCI or GND, IO = 0 5V 0V VI = VCCI or GND, IO = 0 One A port at VCCA - 0.6 V, DIR at VCCA, B port = open DIR at VCCA - 0.6 V, B port = open, A port at VCCA or GND One B port at VCCB - 0.6 V, DIR at GND, A port = open VI = VCCA or GND VO = VCCA/B or GND 1.65 V to 5.5 V VCCB 1.65 V to 4.5 V 1.65 V 2.3 V 3V 4.5 V 1.65 V to 4.5 V 1.65 V 2.3 V 3V 4.5 V 1.65 V to 5.5 V 0 to 5.5 V 0V 1.65 V to 5.5 V 1.65 V to 5.5 V 0V 5V 1.65 V to 5.5 V 0V 5V 1.65 V to 5.5 V 1 1 1 1 TA = 25C MIN TYP MAX -40C to 85C MIN VCCO - 0.1 1.2 1.9 2.4 3.8 0.1 0.45 0.3 0.55 0.55 2 2 2 2 3 2 -2 3 -2 2 4 50 3 V to 5.5 V 3 V to 5.5 V 50 3 V to 5.5 V 3.3 V 3.3 V 3 V to 5.5 V 3.3 V 3.3 V 2.5 6 50 A pF pF A A A A A A A V V MAX UNIT VCCO is the VCC associated with the output port. VCCI is the VCC associated with the input port. Submit Documentation Feedback 5 SN74LVC2T45 DUAL-BIT DUAL-SUPPLY BUS TRANSCEIVER WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS SCES516I - DECEMBER 2003 - REVISED MARCH 2007 www.ti.com Switching Characteristics over recommended operating free-air temperature range, VCCA = 1.8 V 0.15 V (unless otherwise noted) (see Figure 1) PARAMETER tPLH tPHL tPLH tPHL tPHZ tPLZ tPHZ tPLZ tPZH (1) tPZL (1) tPZH (1) tPZL (1) (1) FROM (INPUT) A B DIR DIR DIR DIR TO (OUTPUT) B A A B A B VCCB = 1.8 V 0.15 V MIN 3 2.8 3 2.8 10.6 7.3 10 6.5 MAX 17.7 14.3 17.7 14.3 30.9 19.7 27.9 19.5 37.2 42.2 37.4 45.2 VCCB = 2.5 V 0.2 V MIN 2.2 2.2 2.3 2.1 10.3 7.5 8.4 7.2 MAX 10.3 8.5 16 12.9 30.5 19.6 14.9 12.6 28.6 27.8 29.9 39 VCCB = 3.3 V 0.3 V MIN 1.7 1.8 2.1 2 10.5 7.5 6.5 4.3 MAX 8.3 7.1 15.5 12.6 30.5 19.5 11.3 9.7 25.2 23.9 27.8 37.6 VCCB = 5 V 0.5 V MIN 1.4 1.7 1.9 1.8 10.7 7 4.1 2.1 MAX 7.2 7 15.1 12.2 29.3 19.4 8.6 7.1 22.2 20.8 26.6 36.3 ns ns ns ns ns ns UNIT The enable time is a calculated value, derived using the formula shown in the enable times section. Switching Characteristics over recommended operating free-air temperature range, VCCA = 2.5 V 0.2 V (unless otherwise noted) (see Figure 1) PARAMETER tPLH tPHL tPLH tPHL tPHZ tPLZ tPHZ tPLZ tPZH (1) tPZL (1) tPZH (1) tPZL (1) (1) FROM (INPUT) A B DIR DIR DIR DIR TO (OUTPUT) B A A B A B VCCB = 1.8 V 0.15 V MIN 2.3 2.1 2.2 2.2 6.6 5.3 10.7 7.8 MAX 16 12.9 10.3 8.5 17.1 12.6 27.9 18.9 29.2 36.4 28.6 30 VCCB = 2.5 V 0.2 V MIN 1.5 1.4 1.5 1.4 7.1 5.2 8.1 6.2 MAX 8.5 7.5 8.5 7.5 16.8 12.5 13.9 11.2 19.7 21.4 21 24.3 VCCB = 3.3 V 0.3 V MIN 1.3 1.3 1.4 1.3 6.8 4.9 5.8 3.6 MAX 6.4 5.4 8 7 16.8 12.3 10.5 8.9 16.9 17.5 18.7 22.2 VCCB = 5 V 0.5 V MIN 1.1 0.9 1 0.9 5.2 4.8 3.5 1.4 MAX 5.1 4.6 7.5 6.2 16.5 12.3 7.6 6.2 13.7 13.8 17.4 21.1 UNIT ns ns ns ns ns ns The enable time is a calculated value, derived using the formula shown in the enable times section. 6 Submit Documentation Feedback www.ti.com SN74LVC2T45 DUAL-BIT DUAL-SUPPLY BUS TRANSCEIVER WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS SCES516I - DECEMBER 2003 - REVISED MARCH 2007 Switching Characteristics over recommended operating free-air temperature range, VCCA = 3.3 V 0.3 V (unless otherwise noted) (see Figure 1) PARAMETER tPLH tPHL tPLH tPHL tPHZ tPLZ tPHZ tPLZ tPZH (1) tPZL (1) tPZH (1) tPZL (1) (1) FROM (INPUT) A B DIR DIR DIR DIR TO (OUTPUT) B A A B A B VCCB = 1.8 V 0.15 V MIN 2.1 2 1.7 1.8 5 3.4 11.2 9.4 MAX 15.5 12.6 8.3 7.1 10.9 8.4 27.3 17.7 26 34.4 23.9 23.5 VCCB = 2.5 V 0.2 V MIN 1.4 1.3 1.3 1.3 5.1 3.7 8 5.6 MAX 8 7 6.4 5.4 10.8 8.4 13.7 11.3 17.7 19.1 16.4 17.8 VCCB = 3.3 V 0.3 V MIN 0.7 0.8 0.7 0.8 5 3.9 5.8 4.3 MAX 5.6 5 5.8 5 10.8 8.1 10.4 8.3 14.1 15.4 13.9 15.8 VCCB = 5 V 0.5 V MIN 0.7 0.7 0.6 0.7 5 3.3 2.9 1 MAX 4.4 4 5.4 4.5 10.4 7.8 7.4 5.6 11 11.9 12.2 14.4 ns ns ns ns ns ns UNIT The enable time is a calculated value, derived using the formula shown in the enable times section. Switching Characteristics over recommended operating free-air temperature range, VCCA = 5 V 0.5 V (unless otherwise noted) (see Figure 1) PARAMETER tPLH tPHL tPLH tPHL tPHZ tPLZ tPHZ tPLZ tPZH (1) tPZL (1) tPZH (1) tPZL (1) (1) FROM (INPUT) A B DIR DIR DIR DIR TO (OUTPUT) B A A B A B VCCB = 1.8 V 0.15 V MIN 1.9 1.8 1.4 1.7 2.9 1.4 11.2 8.4 MAX 15.1 12.2 7.2 7 8.2 6.9 26.1 16.9 24.1 33.1 22 20.4 VCCB = 2.5 V 0.2 V MIN 1 0.9 1 0.9 2.9 1.3 7.2 5 MAX 7.5 6.2 5.1 4.6 7.9 6.7 13.9 11 16.1 18.5 14.2 14.1 VCCB = 3.3 V 0.3 V MIN 0.6 0.7 0.7 0.7 2.8 0.7 5.8 4 MAX 5.4 4.5 4.4 4 7.9 6.7 10.1 7.7 12.1 14.1 12.1 12.4 VCCB = 5 V 0.5 V MIN 0.5 0.5 0.5 0.5 2.2 0.7 1.3 1 MAX 3.9 3.5 3.9 3.5 7.8 6.6 7.3 5.6 9.5 10.8 10.5 11.3 UNIT ns ns ns ns ns ns The enable time is a calculated value, derived using the formula shown in the enable times section. Submit Documentation Feedback 7 SN74LVC2T45 DUAL-BIT DUAL-SUPPLY BUS TRANSCEIVER WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS SCES516I - DECEMBER 2003 - REVISED MARCH 2007 www.ti.com Operating Characteristics TA = 25C PARAMETER A-port input, B-port output B-port input, A-port output A-port input, B-port output B-port input, A-port output TEST CONDITIONS CL = 0 pF, f = 10 MHz, tr = tf = 1 ns CL = 0 pF, f = 10 MHz, tr = tf = 1 ns VCCA = VCCB = 1.8 V TYP 3 18 18 3 VCCA = VCCB = 2.5 V TYP 4 19 19 4 VCCA = VCCB = 3.3 V TYP 4 20 20 4 VCCA = VCCB = 5 V TYP 4 pF 21 21 pF 4 UNIT CpdA (1) CpdB (1) (1) Power dissipation capacitance per transceiver 8 Submit Documentation Feedback www.ti.com SN74LVC2T45 DUAL-BIT DUAL-SUPPLY BUS TRANSCEIVER WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS SCES516I - DECEMBER 2003 - REVISED MARCH 2007 Power-Up Considerations A proper power-up sequence always should be followed to avoid excessive supply current, bus contention, oscillations, or other anomalies. To guard against such power-up problems, take the following precautions: 1. Connect ground before any supply voltage is applied. 2. Power up VCCA. 3. VCCB can be ramped up along with or after VCCA. Table 1. Typical Total Static Power Consumption (ICCA + ICCB) VCCB 0V 1.8 V 2.5 V 3.3 V 5V VCCA 0V 0 <1 <1 <1 <1 1.8 V <1 <2 <2 <2 2 2.5 V <1 <2 <2 <2 <2 3.3 V <1 <2 <2 <2 <2 5V <1 2 <2 <2 <2 A UNIT Submit Documentation Feedback 9 SN74LVC2T45 DUAL-BIT DUAL-SUPPLY BUS TRANSCEIVER WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS SCES516I - DECEMBER 2003 - REVISED MARCH 2007 www.ti.com TYPICAL CHARACTERISTICS abc TYPICAL PROPAGATION DELAY (A to B) vs LOAD CAPACITANCE TA = 25C, VCCA = 1.8 V 10 9 8 VCCB = 1.8 V 7 t PLH- ns 6 5 4 3 2 1 0 0 5 10 15 20 25 30 35 CL - pF VCCB = 3.3 V VCCB = 5 V VCCB = 2.5 V 7 6 5 4 VCCB = 5 V 3 2 1 0 0 5 10 15 20 25 30 35 CL - pF VCCB = 2.5 V VCCB = 3.3 V 10 9 8 VCCB = 1.8 V t PHL - ns TYPICAL PROPAGATION DELAY (B to A) vs LOAD CAPACITANCE TA = 25C, VCCA = 1.8 V 10 9 8 VCCB = 1.8 V 7 6 5 4 3 2 1 0 0 5 10 15 20 CL - pF 25 30 35 VCCB = 2.5 V VCCB = 3.3 V VCCB = 5 V 7 6 5 4 3 2 1 0 0 5 10 15 20 CL - pF 25 30 35 VCCB = 3.3 V VCCB = 5 V 10 9 8 VCCB = 1.8 V VCCB = 2.5 V 10 Submit Documentation Feedback t PLH - ns t PHL - ns www.ti.com SN74LVC2T45 DUAL-BIT DUAL-SUPPLY BUS TRANSCEIVER WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS SCES516I - DECEMBER 2003 - REVISED MARCH 2007 TYPICAL CHARACTERISTICS abc TYPICAL PROPAGATION DELAY (A to B) vs LOAD CAPACITANCE TA = 25C, VCCA = 2.5 V 10 9 8 7 t PHL - ns 6 5 VCCB = 2.5 V 4 3 2 1 0 0 5 10 15 20 25 30 35 CL - pF VCCB = 3.3 V VCCB = 5 V VCCB = 1.8 V t PLH - ns 10 9 8 7 6 5 4 3 2 1 0 0 5 10 15 20 25 30 35 CL - pF VCCB = 2.5 V VCCB = 3.3 V VCCB = 5 V VCCB = 1.8 V TYPICAL PROPAGATION DELAY (B to A) vs LOAD CAPACITANCE TA = 25C, VCCA = 2.5 V 10 9 8 7 t PHL - ns t PLH - ns 6 5 4 3 VCCB = 2.5 V 2 1 0 VCCB = 3.3 V VCCB = 5 V VCCB = 1.8 V 10 9 8 7 6 5 4 3 2 1 0 VCCB = 2.5 V VCCB = 3.3 V VCCB = 5 V VCCB = 1.8 V 0 5 10 15 20 CL - pF 25 30 35 0 5 10 15 20 25 30 35 CL - pF Submit Documentation Feedback 11 SN74LVC2T45 DUAL-BIT DUAL-SUPPLY BUS TRANSCEIVER WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS SCES516I - DECEMBER 2003 - REVISED MARCH 2007 www.ti.com TYPICAL CHARACTERISTICS abc TYPICAL PROPAGATION DELAY (A to B) vs LOAD CAPACITANCE TA = 25C, VCCA = 3.3 V 10 9 8 7 6 t PLH - ns t PHL - ns 5 4 3 2 VCCB = 3.3 V 1 0 0 5 10 15 20 25 30 35 CL - pF 1 VCCB = 5 V 0 0 5 10 15 20 25 30 35 CL - pF VCCB = 2.5 V 10 9 8 7 VCCB = 1.8 V 6 5 4 3 2 VCCB = 5 V VCCB = 2.5 V VCCB = 1.8 V VCCB = 3.3 V TYPICAL PROPAGATION DELAY (B to A) vs LOAD CAPACITANCE TA = 25C, VCCA = 3.3 V 10 9 8 7 6 t PHL - ns t PLH - ns 5 VCCB = 1.8 V 4 3 2 1 0 0 5 10 15 CL - pF 20 25 30 35 VCCB = 2.5 V VCCB = 3.3 V VCCB = 5 V 10 9 8 7 6 5 4 3 2 1 0 0 5 10 15 CL - pF 20 25 30 35 VCCB = 2.5 V VCCB = 3.3 V VCCB = 5 V VCCB = 1.8 V 12 Submit Documentation Feedback www.ti.com SN74LVC2T45 DUAL-BIT DUAL-SUPPLY BUS TRANSCEIVER WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS SCES516I - DECEMBER 2003 - REVISED MARCH 2007 TYPICAL CHARACTERISTICS abc TYPICAL PROPAGATION DELAY (A to B) vs LOAD CAPACITANCE TA = 25C, VCCA = 5 V 10 9 8 7 VCCB = 1.8 V t PLH - ns 6 t PHL - ns 5 4 3 2 VCCB = 3.3 V 1 0 0 5 VCCB = 5 V 10 15 20 25 30 35 1 0 0 5 10 15 CL - pF 20 25 30 35 CL - pF VCCB = 2.5 V 10 9 8 VCCB = 1.8 V 7 6 5 VCCB = 2.5 V 4 VCCB = 3.3 V 3 VCCB = 5 V 2 TYPICAL PROPAGATION DELAY (B to A) vs LOAD CAPACITANCE TA = 25C, VCCA = 5 V 10 9 8 7 6 t PHL- ns 5 4 3 2 1 0 0 5 10 15 20 25 30 35 CL - pF VCCB = 3.3 V VCCB = 5 V VCCB = 1.8 V VCCB = 2.5 V 10 9 8 7 6 t PLH - ns 5 VCCB = 1.8 V 4 VCCB = 2.5 V 3 2 VCCB = 3.3 V 1 0 0 5 10 15 20 25 30 35 CL - pF VCCB = 5 V Submit Documentation Feedback 13 SN74LVC2T45 DUAL-BIT DUAL-SUPPLY BUS TRANSCEIVER WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS SCES516I - DECEMBER 2003 - REVISED MARCH 2007 www.ti.com PARAMETER MEASUREMENT INFORMATION 2 x VCCO From Output Under Test CL (see Note A) RL RL S1 Open GND TEST tpd tPLZ/tPZL tPHZ/tPZH S1 Open 2 x VCCO GND LOAD CIRCUIT tw VCCI Input VCCI/2 VCCI/2 0V VOLTAGE WAVEFORMS PULSE DURATION VCCO 1.8 V 0.15 V 2.5 V 0.2 V 3.3 V 0.3 V 5 V 0.5 V CL 15 pF 15 pF 15 pF 15 pF RL 2 k 2 k 2 k 2 k VTP 0.15 V 0.15 V 0.3 V 0.3 V Output Control (low-level enabling) tPZL VCCI Output Waveform 1 S1 at 2 x VCCO (see Note B) tPZH Output Waveform 2 S1 at GND (see Note B) VCCA VCCA/2 VCCA/2 0V tPLZ VCCO VCCO/2 VOL + VTP VOL tPHZ VOH - VTP VOH 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES Input VCCI/2 VCCI/2 0V tPLH tPHL VOH VCCO/2 VOL Output VCCO/2 VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES VCCO/2 NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR v10 MHz, ZO = 50 , dv/dt 1 V/ns. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. H. VCCI is the VCC associated with the input port. I. VCCO is the VCC associated with the output port. J. All parameters and waveforms are not applicable to all devices. Figure 1. Load Circuit and Voltage Waveforms 14 Submit Documentation Feedback www.ti.com SN74LVC2T45 DUAL-BIT DUAL-SUPPLY BUS TRANSCEIVER WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS SCES516I - DECEMBER 2003 - REVISED MARCH 2007 APPLICATION INFORMATION The following shows an example of the SN74LVC2T45 being used in a unidirectional logic level-shifting application. VCC1 VCC1 1 2 3 4 VCC1 8 7 6 5 VCC2 VCC2 VCC2 SYSTEM-1 SYSTEM-2 PIN 1 2 3 4 5 6 7 8 NAME VCCA A1 A2 GND DIR B2 B1 VCCB FUNCTION VCC1 OUT1 OUT2 GND DIR IN2 IN1 VCC2 DESCRIPTION SYSTEM-1 supply voltage (1.65 V to 5.5 V) Output level depends on VCC1 voltage. Output level depends on VCC1 voltage. Device GND GND (low level) determines B-port to A-port direction. Input threshold value depends on VCC2 voltage. Input threshold value depends on VCC2 voltage. SYSTEM-2 supply voltage (1.65 V to 5.5 V) Figure 2. Unidirectional Logic Level-Shifting Application Submit Documentation Feedback 15 SN74LVC2T45 DUAL-BIT DUAL-SUPPLY BUS TRANSCEIVER WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS SCES516I - DECEMBER 2003 - REVISED MARCH 2007 www.ti.com APPLICATION INFORMATION Figure 3 shows the SN74LVC2T45 being used in a bidirectional logic level-shifting application. Since the SN74LVC2T45 does not have an output-enable (OE) pin, the system designer should take precautions to avoid bus contention between SYSTEM-1 and SYSTEM-2 when changing directions. VCC1 Pullup/Down or Bus Hold(1) 1 2 3 4 8 7 6 5 VCC1 VCC2 Pullup/Down or Bus Hold(1) VCC2 I/O-1 I/O-2 DIR CTRL SYSTEM-1 SYSTEM-2 The following table shows data transmission from SYSTEM-1 to SYSTEM-2 and then from SYSTEM-2 to SYSTEM-1. STATE 1 2 3 4 (1) DIR CTRL H H L L I/O-1 Out Hi-Z Hi-Z In I/O-2 In Hi-Z Hi-Z Out SYSTEM-1 data to SYSTEM-2 SYSTEM-2 is getting ready to send data to SYSTEM-1. I/O-1 and I/O-2 are disabled. The bus-line state depends on pullup or pulldown. (1) DIR bit is flipped. I/O-1 and I/O-2 still are disabled. The bus-line state depends on pullup or pulldown. (1) SYSTEM-2 data to SYSTEM-1 DESCRIPTION SYSTEM-1 and SYSTEM-2 must use the same conditions, i.e., both pullup or both pulldown. Figure 3. Bidirectional Logic Level-Shifting Application Enable Times Calculate the enable times for the SN74LVC2T45 using the following formulas: * tPZH (DIR to A) = tPLZ (DIR to B) + tPLH (B to A) * tPZL (DIR to A) = tPHZ (DIR to B) + tPHL (B to A) * tPZH (DIR to B) = tPLZ (DIR to A) + tPLH (A to B) * tPZL (DIR to B) = tPHZ (DIR to A) + tPHL (A to B) In a bidirectional application, these enable times provide the maximum delay from the time the DIR bit is switched until an output is expected. For example, if the SN74LVC2T45 initially is transmitting from A to B, then the DIR bit is switched; the B port of the device must be disabled before presenting it with an input. After the B port has been disabled, an input signal applied to it appears on the corresponding A port after the specified propagation delay. 16 Submit Documentation Feedback PACKAGE OPTION ADDENDUM www.ti.com 15-Mar-2007 PACKAGING INFORMATION Orderable Device SN74LVC2T45DCTR SN74LVC2T45DCTRE4 SN74LVC2T45DCTT SN74LVC2T45DCTTE4 SN74LVC2T45DCUR SN74LVC2T45DCURE4 SN74LVC2T45DCURG4 SN74LVC2T45DCUT SN74LVC2T45DCUTE4 SN74LVC2T45YZPR (1) Status (1) ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE Package Type SM8 SM8 SM8 SM8 US8 US8 US8 US8 US8 WCSP Package Drawing DCT DCT DCT DCT DCU DCU DCU DCU DCU YZP Pins Package Eco Plan (2) Qty 8 8 8 8 8 8 8 8 8 8 3000 3000 250 250 Pb-Free (RoHS) Pb-Free (RoHS) Pb-Free (RoHS) Pb-Free (RoHS) Lead/Ball Finish CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU SNAGCU MSL Peak Temp (3) Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM 3000 Green (RoHS & no Sb/Br) 3000 Green (RoHS & no Sb/Br) 3000 Green (RoHS & no Sb/Br) 250 250 Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) 3000 Green (RoHS & no Sb/Br) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 MECHANICAL DATA MPDS049B - MAY 1999 - REVISED OCTOBER 2002 DCT (R-PDSO-G8) 0,30 0,15 8 5 PLASTIC SMALL-OUTLINE PACKAGE 0,65 0,13 M 0,15 NOM 2,90 2,70 4,25 3,75 PIN 1 INDEX AREA 0,10 0,00 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion Falls within JEDEC MO-187 variation DA. CCCCC CCCCC CCCCC CCCCC 1 3,15 2,75 Gage Plane 0,25 4 0 - 8 0,60 0,20 1,30 MAX Seating Plane 0,10 4188781/C 09/02 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI's terms and conditions of sale supplied at the time of order acknowledgment. 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