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	HEF4518BN
	Philips Semiconductors
	Dual counter
	67.76 千字节
	7 页
	Maker Site: http://www.nxp.com/
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HEF4518BN DataSheet Philips Semiconductors Dual BCD counter

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HEF4518 HEF4518B HEF4518BD HEF4518BF HEF4518BN HEF4518BP HEF4518BT
HEF4518BP

HEF4518	[Philips Semiconductors] Dual BCD counter
HEF4518B	[Philips Semiconductors] Dual BCD counter
HEF4518BD	[Philips Semiconductors] Dual BCD counter
HEF4518BF	[Philips Semiconductors] Dual BCD counter
HEF4518BN	[Philips Semiconductors] Dual BCD counter
HEF4518BP	[Philips Semiconductors] Dual BCD counter
HEF4518BT	[Philips Semiconductors] Dual BCD counter
HEF4518B	[Philips] Dual BCD counter
HEF4518BPNNBSP	[Philips Semiconductors] Synchronous Up Counter
HEF4518BPNBSP	[Philips Semiconductors] Synchronous Up Counter
HEF4518BP	[PHILIPS] Dual BCD counter
HEF4518BP	[] From old datasheet system
HEF4518BT	[PHILIPS[Philips Semiconductors]] Dual BCD counter
HEF4518	[PHILIPS[Philips Semiconductors]] Dual BCD counter
HEF4518B	[PHILIPS[Philips Semiconductors]] Dual BCD counter
HEF4518BD	[PHILIPS[Philips Semiconductors]] Dual BCD counter
HEF4518BF	[PHILIPS[Philips Semiconductors]] Dual BCD counter
HEF4518BN	[PHILIPS[Philips Semiconductors]] Dual BCD counter

INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
* The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC * The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC
HEF4518B MSI Dual BCD counter
Product specification File under Integrated Circuits, IC04 January 1995
Philips Semiconductors
Product specification
Dual BCD counter
DESCRIPTION T he HEF4518B is a dual 4-bit internally synchronous BCD counter. The counter has an active HIGH clock input (CP0) and an active LOW clock input (CP1), buffered outputs from all four bit positions (O0 to O3) and an active HIGH overriding asynchronous master reset input (MR). The counter advances on either the LOW to HIGH transition of the CP0 input if CP1 is HIGH or the HIGH to
HEF4518B MSI
LOW transition of the CP1 input if CP0 is LOW. Either CP0 or CP1 may be used as the clock input to the counter and the other clock input may be used as a clock enable input. A HIGH on MR resets the counter (O0 to O3 = LOW) independent of CP0, CP1. Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times.
Fig.2 Pinning diagram.
HEF4518BP(N): HEF4518BD(F): HEF4518BT(D):
16-lead DIL; plastic (SOT38-1) 16-lead DIL; ceramic (cerdip) (SOT74) 16-lead SO; plastic (SOT109-1)
( ): Package Designator North America Fig.1 Functional diagram.
PINNING CP0A, CP0B CP1A, CP1B MRA, MRB O0A to O3A O0B to O3B clock inputs (L to H triggered) clock inputs (H to L triggered) master reset inputs outputs outputs
APPLICATION INFORMATION Some examples of applications for the HEF4518B are: * Multistage synchronous counting. * Multistage asynchronous counting. * Frequency dividers. FAMILY DATA, IDD LIMITS category MSI See Family Specifications
January 1995
2
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Dual BCD counter HEF4518B MSI
Philips Semiconductors
Product specification
Dual BCD counter
AC CHARACTERISTICS VSS = 0 V; Tamb = 25 C; CL = 50 pF; input transition times  20 ns VDD V Propagation delays CP0 , CP1  On HIGH to LOW 5 10 15 5 LOW to HIGH MR  On HIGH to LOW Output transition times HIGH to LOW 5 10 15 5 LOW to HIGH Minimum CP0 pulse width; LOW Minimum CP1 pulse width; HIGH Minimum MR pulse width; HIGH Recovery time for MR Set-up times CP0  CP1 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 CP1  CP0 Maximum clock pulse frequency 10 15 5 10 15 January 1995 fmax tsu tsu tRMR tWMRH tWCPH tWCPL 60 30 20 60 30 20 30 20 16 50 30 20 50 30 20 50 30 20 8 15 20 4 tTLH tTHL 60 30 20 60 30 20 30 15 10 30 15 10 15 10 8 25 15 10 25 15 10 25 15 10 16 30 40 120 ns 60 ns 40 ns 120 ns 60 ns 40 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz MHz MHz 10 15 5 10 15 tPHL tPLH tPHL 120 55 40 120 55 40 75 35 25 240 ns 110 ns 80 ns 240 ns 110 ns 80 ns 150 ns 70 ns 50 ns SYMBOL MIN. TYP. MAX.
HEF4518B MSI
TYPICAL EXTRAPOLATION FORMULA 93 ns + (0,55 ns/pF) CL 44 ns + (0,23 ns/pF) CL 32 ns + (0,16 ns/pF) CL 93 ns + (0,55 ns/pF) CL 44 ns + (0,23 ns/pF) CL 32 ns + (0,16 ns/pF) CL 48 ns + (0,55 ns/pF) CL 24 ns + (0,23 ns/pF) CL 17 ns + (0,16 ns/pF) CL 10 ns + (1,0 ns/pF) CL 9 ns + (0,42 ns/pF) CL 6 ns + (0,28 ns/pF) CL 10 ns + (1,0 ns/pF) CL 9 ns + (0,42 ns/pF) CL 6 ns + (0,28 ns/pF) CL
see also waveforms Figs 4 and 5
Philips Semiconductors
Product specification
Dual BCD counter
AC CHARACTERISTICS VSS = 0 V; Tamb = 25 C; input transition times  20 ns VDD V Dynamic power dissipation per package (P) 5 10 15 TYPICAL FORMULA FOR P (W) 750fi +  (foCL) x VDD2 3300 fi +  (foCL) x VDD
2
HEF4518B MSI
where fi = input freq. (MHz) fo = output freq. (MHz) CL = load capacitance (pF)  (foCL) = sum of outputs VDD = supply voltage (V)
8000 fi +  (foCL) x VDD2
Fig.4 Waveforms showing recovery time for MR; minimum CP0, CP1 and MR pulse widths.
January 1995
5
Philips Semiconductors
Product specification
Dual BCD counter
HEF4518B MSI
Fig.5 Waveforms showing set-up times for CP0 to CP1 and CP1 to CP0, and propagation delays.
January 1995
6
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Dual BCD counter HEF4518B MSI